1. Field of the Invention
This invention relates generally to semiconductor manufacturing structures and techniques, and, more particularly, to a structure useful in detecting erroneous electrical connections in a semiconductor device.
2. Description of the Related Art
Integrated circuits, or microchips, are manufactured from modem semiconductor devices containing numerous structures or features, typically the size of a few micrometers. The features are placed in localized areas of a semiconducting substrate, and are conductive, non-conductive, or semi-conductive (i.e., rendered conductive in defined areas with dopants). The fabrication process generally involves processing a number of wafers through a series of fabrication tools. Each fabrication tool performs one or more of four basic operations discussed more fully below. The four basic operations are performed in accordance with an overall process to produce wafers from which the semiconductor devices are obtained.
Integrated circuits are manufactured from wafers of a semiconducting substrate material. Layers of materials are added, removed, and/or treated during fabrication to create the integrated electrical circuits that make up the device. The fabrication essentially comprises the following four basic operations:
layering, or adding thin layers of various materials to a wafer from which a semiconductor is produced;
patterning, or removing selected portions of added layers;
doping, or placing specific amounts of dopants in selected portions of the wafer through openings in the added layers; and
heat treating, or heating and cooling the materials to produce desired effects in the processed wafer.
Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process. See, e.g., Peter Van Zant, Microchip Fabrication A Practical Guide to Semiconductor Processing (3d Ed. 1997 McGraw-Hill Companies, Inc.) (ISBN 0-07-067250-4).
The integrated circuits must be patterned in the precise dimensions required by the circuit design and located in their proper place on the wafer. Forming parts with such precise dimensions implicates what is known as xe2x80x9ccritical dimension control.xe2x80x9d xe2x80x9cCritical dimensionsxe2x80x9d include, among other things, the line widths of the electrically conductive traces and the width of the insulating materials between the traces that define the pattern. Critical dimension control ensures that portions of the pattern containing critical dimensions are formed precisely. Locating the parts in their proper place implicates what is known as xe2x80x9coverlay control,xe2x80x9d i.e., ensuring that the pattern being fabricated is properly aligned relative to previously formed patterns. This is accomplished by ensuring that a reticle (or mask) used in forming the pattern being fabricated is properly aligned with the wafer prior to beginning the processing operation. Simply put, overlay control ensures that the reticle precisely overlays, or is aligned with, the wafer.
Proper alignment and dimension control are necessary to avoid failure of the electrical circuits employed across an integrated circuit. For instance, if vias (i.e., conductive plugs or openings between layers) are not properly positioned over electrically conductive traces, parts of the circuit that should electrically communicate with each other may actually be electrically isolated from each other. Even if this extreme scenario does not occur, slight misalignment or poor dimensioning may cause devices to receive voltages or currents that are less than the designed or targeted amount, thereby degrading device performance.
Critical dimension control and overlay control are also important because successive steps of the fabrication process tend to be interdependent. A slight variation in the parameter(s) of one process step can be compounded by a variation in the parameters of a second process step to produce unacceptable numbers of defective product at the output end of the mass-production line. The efficacy of critical dimension control and overlay control are also interdependent. For instance, overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device.
Generally, minimization of misalignment errors is important to ensure that the multiple layers of the semiconductor devices are connected and functional. As technology facilitates smaller critical dimensions for semiconductor devices, the need for reduced misalignment errors increases dramatically to ensure functional circuits.
Microscopic dimensional capabilities of current semiconductor manufacturing equipment make possible the design of digital circuits that may be very complex and yet extremely economical in space, power requirements and cost. At the same time, however, the microscopic dimensions of current semiconductor manufacturing also amplifies the effects of even small errors or mistakes in the manufacturing process. Sometimes, an error or mistake can cause major economic loss. It is therefore important to discover, not only that there are defects in the wafer manufacturing process, but also exactly what is causing those defects. Because of the complexities in design and fabrication, considerable effort goes into testing.
One particular form of failure analysis is commonly referred to as xe2x80x9cvoltage contrast analysis.xe2x80x9d In this form of analysis, the surface of the wafer is charged, and the charge patterns of various die on the wafer are compared. More particularly, the wafer is scanned by a scanning electron microscope (xe2x80x9cSEMxe2x80x9d). The light beam charges the insulators and ungrounded conductors, but does not charge the grounded conductors, as any charge is dissipated through the ground connection. When the scanned wafer surface is examined with the SEM, the charged insulator will appear light, or white, and the uncharged conductors appear dark, or black. Several individual die, typically three, are then examined simultaneously using a pattern-recognition and matching technique. If two of the three match, the third die is flagged as defective on the assumption the process performs reliably. A variety of commercially available tools perform this type of analysis, including the SEMSpec Metrology Tool available from KLA-Tencor, Inc., 160 Rio Robles, San Jose, Calif. 95134, USA.
FIGS. 1A and 1B further illustrate voltage contrast analysis. FIGS. 1A and 1B illustrate, in cross-section, portions of two die 100, 120 that were designed to be substantially identical, but owing to variations in the manufacturing process, are different. The two die 100, 120 each consist of five layers 102, 104, 106, 108, and 110. Each of the layers 102, 104, 106, and 108 comprises conducting portions 112 and insulating portions 114. The layer 110 is a conductor 112 serving as a ground plane. The conducting portion 112 of the layer 106 does not contact the conducting portion 112 of the layer 108 in the die 100, but does so in the die 120. Thus, the conducting portions 112 in the die 120 are grounded, but the conducting portions 112 in the layers 102, 104, and 106 of the die 100 are not, i. e., they xe2x80x9cfloat.xe2x80x9d When scanned by an SEM (not shown), the conducting portion 112 in the layer 102 of the die 100 will charge, and will appear white during the examination. The same conducting portion 112 in the layer 102 of the die 120 will not charge, because it is grounded, and will appear black during the examination.
This voltage contrast analysis suffers from several drawbacks, however. The approach of comparing like die to detect improper electrical connections has proven problematic, owing to its inability to detect common errors. That is, where the same improper electrical connection exists in all of the analyzed semiconductor die, comparing the voltage contrast of the die will not result in the improper electrical connection being detected. Owing to the repetitive nature of the manufacturing process, when an error, such as misalignment, has occurred in one wafer, it is likely to be replicated in many other wafers. Thus, comparing like wafers may fail to reveal like errors.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method is used to test a semiconductor wafer. The method comprises forming a plurality of electrically conductive connections on a surface of a semiconductor wafer. A portion of the electrically conductive connections are coupled to a voltage supply. Thereafter, a voltage contrast analysis of the surface of the semiconductor wafer is performed, and a first pattern of the plurality of electrically conductive connections coupled to the voltage supply is determined from the voltage contrast analysis. The method further comprises comparing the first pattern to a desired pattern, and indicating an error in response to the first pattern differing from the desired pattern.
In another aspect of the present invention, a test structure is formed on a semiconductor wafer. The test structure comprises a plurality of electrically conductive connections arranged in an nxc3x97m array on a surface of the semiconductor wafer, an electrically conductive substrate; and a first and second plurality of electrical interconnections. The first plurality of electrical interconnections extends between at least a portion of the electrically conductive connections and the electrically conductive substrate in a preselected pattern, wherein the first plurality of electrical interconnections are capable of removing charge introduced to the electrically conductive connections during a voltage contrast analysis. The second plurality of electrical interconnections extends partially between at least a portion of the electrically conductive connections and the electrically conductive substrate in a preselected pattern.
In another aspect of the present invention, a system for identifying misaligned layers in a semiconductor wafer is provided. The system comprises a voltage contrast metrology tool and a controller. The voltage contrast metrology tool is capable of performing a voltage contrast analysis on a region of a surface of the semiconductor wafer. The region comprises a plurality of electrically conductive connections, at least a portion of which are coupled to a power supply. The voltage contrast metrology tool determines a first preselected pattern of the electrically conductive connections coupled to the power supply. The controller is capable of comparing the first preselected pattern to a desired pattern, and indicating the presence of a misaligned layer in response to detecting a difference there between.